DFT Senior Engineer
DFT Senior Engineer
Broadcom- Posted a day ago
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Job Description
Job Description:
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
The candidate should have in-depth knowledge of DFT concepts and should be experienced in various aspects of DFT -ATPG, MBIST & IJTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage.
Experience with either Mentor Graphics DFT tools (Tessent Shell) is highly desirable.
The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently. The candidate should possess excellent communication skills.
Educational qualification & Experience Level : Bachelor's degree with 5+ years of relevant experience or Master's degree with 3+ years of relevant experience
R027637
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
The candidate should have in-depth knowledge of DFT concepts and should be experienced in various aspects of DFT -ATPG, MBIST & IJTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage.
Experience with either Mentor Graphics DFT tools (Tessent Shell) is highly desirable.
The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently. The candidate should possess excellent communication skills.
Educational qualification & Experience Level : Bachelor's degree with 5+ years of relevant experience or Master's degree with 3+ years of relevant experience
R027637
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Key Skills
About Company
Skills:
Scripting Languages, Shell, Perl, DFT concepts, Yield improvement, MBIST, Test insertion, Coverage improvement, Verification, Post silicon debug, Tessent Shell, ATPG, Mentor Graphics DFT tools, Pattern generation, Vector simulation, IJTAG, DFT Architecture
Skills:
DFT DRC, DFT architecture, Scan Insertion, MBIST Implementation, SoC-level DFT Integration, ATPG, Fault Coverage Analysis, Scan Compression, JTAG IEEE 1149.1, Debug
Skills:
Perl, Python, Tcl, scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG
Skills:
hardware description languages (HDLs), Jtag, BSDL standards, DFT IP development, MBIST, DFT methodology, Test clocking requirements, simulation methodologies, silicon debugs, ATPG, Simulation environments, ASIC DFT Implementation tools, Test mode timing closure, Scan, MBIST implementation, Shmoo, DFT Architecture
Skills:
boundary scan , Debugging, Tessent tools, coverage analysis, clock analog observe PLL RO, DFT – Scan ATPG, thermal sensors, SSN EDT, JTAG networks, DFX DV for IP debug units, TDR verification, clock-stop features, scan pattern generation, test-case development, AFM fault models, scan pattern simulation, root-cause analysis