DFT Manager
Search Jobs
Search by job, company or skills
Search by job, company or skills
This job is no longer accepting applications
Position: DFT Lead/Manager/Staff Engineers
Experience: 10 to 15 relevant experience.
Location - Bangalore, Hyderabad
To Be Successful In This Role You Will
Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design for Test skills and Tools .
Technical Skillset Required
Note: We are hiring for Lead/Manager/Staff Engineer.
About Us
Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions.
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide.
Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.
Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one's intellect, skills and growth.
Interested candidates can drop their or referred resume to [Confidential Information] or whatsapp to 8431158236/9567490263 (Nishkal)
Job ID: 151581583
Skills:
shell scripting, Spyglass DFT, Memory Repair BIRA BISR circuitry, X86 CPU architecture and microarchitecture, JTAG Memory BIST, advanced process nodes and hierarchical DFT strategies, DFT Design and verification using RTL simulations and emulation, RTL Coding, timing constraints and DFT mode timing analysis
Skills:
Jtag, Perl, Python, Tcl, MBIST, Siemens Tessent, Synopsys TestMAX SMS, DFT protocols, iJTAG, IEEE 1687, SoC DFT architecture and design, Cadence Modus, EDA Tools, Scan Compression, IEEE 1149.1, LBIST
Skills:
Synopsys, MBIST, physical design flows, Synthesis, test-mode integration, ATPG, DFT ATPG tools, cdc, Dft, Rtl Design, Scan Insertion, Cadence
Skills:
DFT verification, DFT Insertion, ATE Pattern Development, DFT concepts, RTL lint tool, BSCAN, MBIST, ATPG Coverage Analysis, equivalence check, ATE support, spyglass, Scan, IJTAG, Netlist level Insertion
Skills:
System Verilog, Jtag, Uvm, GLS, MBIST, LEC, ATPG, Scan Architectures, VMM, IJTAG, DFX, Coverage, Dft
