Jtag, DFT Engineer, DFT Manager, iJTAG, BSCAN, ATPG, technical ownership, DFT tools

SpyGlass DFT, Siemens Tessent, Synopsys TestMAX

Tcl, Python, Perl, SoC DFT architecture and design

automation, Synthesis, cdc, verification processes, physical design flows, MBIST, test-mode integration, methodology enhancements, Rtl Design, Dft, ATPG, silicon bring-up, production test, DFT architecture planning

System Verilog, Jtag, Uvm, GLS, MBIST, LEC, ATPG, Scan Architectures, VMM, IJTAG, DFX, Coverage, Dft

DFT verification, DFT Insertion, ATE Pattern Development, DFT concepts, RTL lint tool, BSCAN, MBIST, ATPG Coverage Analysis, equivalence check, ATE support, spyglass, Scan, IJTAG, Netlist level Insertion

test coverage , Jtag, gate-level, stuck-at, memory test strategies, full scan compression, BSCAN, debug RTL, DFT simulation, Cadence, MBIST, transition at-speed, iJTAG, SoC test architecture, test quality metrics, ATPG, Siemens, industry DFT tools, Synopsys, Scan architectures, hierarchical DFT