DFT Lead
Experience: 10+ Years
Location: Bengaluru, India
Employment Type: Full-Time
Role Overview
We are looking for a highly experienced DFT Engineerto lead and define Design-for-Test strategies for complex SoC designs. The ideal candidate will own DFT architecture decisions, drive implementation across IPs and SoCs, and work closely with RTL, PD, verification, and silicon teams to ensure high test coverage, yield, and manufacturability.
Key Responsibilities
DFT Architecture & Strategy
- Define end-to-end DFT architecture for complex SoCs and subsystems.
- Own and drive DFT strategy, including Scan, ATPG, MBIST, Logic BIST, and Boundary Scan.
- Make architecture-level trade-offs considering area, power, timing, and test coverage.
MBIST / BIST / ATPG
- Architect and implement MBIST solutions for SRAMs, ROMs, and embedded memories.
- Define and deploy Logic BIST / BIST strategies for IPs and SoCs.
- Drive ATPG flow, fault models, coverage closure, and pattern optimization.
- Review and sign off on test coverage, pattern counts, and test quality metrics.
SoC Integration & Execution
- Lead Scan insertion, compression, IJTAG (1687), and hierarchical DFT integration.
- Ensure smooth DFT integration across multiple IPs and third-party blocks.
- Collaborate with PD teams to resolve DFT-related timing, congestion, and power issues.
- Support post-silicon debug, yield learning, and failure analysis.
Cross-Functional Leadership
- Act as the DFT technical authority for programs.
- Mentor and guide junior DFT engineers.
- Work closely with RTL, DV, PD, AMS, and manufacturing teams.
- Interface with EDA vendors and foundry teams on DFT methodologies and best practices.
Required Skills & Experience
Technical Expertise
- 10+ years of hands-on experience in DFT for SoC designs.
- Strong expertise in MBIST, ATPG, Scan, Logic BIST, and DFT sign-off.
- Experience with DFT architecture definition at IP and SoC level.
- Solid understanding of fault models, coverage metrics, and yield concepts.
- Experience with low-power DFT, clocking, reset, and test mode handling.
Tools & Methodologies
- Proficiency with industry-standard DFT tools (Synopsys / Cadence / Siemens).
- Experience with DFT Compiler, Tessent, Modus, or equivalent tools.
- Familiarity with IJTAG (IEEE 1687) and Boundary Scan (1149.x).
- Scripting skills in TCL / Python / Perl for flow automation.
Good to Have
- Experience in advanced technology nodes (7nm, 5nm, 3nm).
- Exposure to automotive, safety-critical, or high-reliability SoCs.
- Knowledge of DFT for low-power and high-speed designs.
- Prior experience in leading DFT teams or multi-project ownership.
Why Join Us
- Work on cutting-edge SoC designs.
- High-impact role with architect-level ownership.
- Collaborative, fast-paced engineering culture.
- Opportunity to mentor teams and shape DFT strategy at scale.
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we're committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
https://www.siliconpatterns.com
