DFT Lead
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Job Requirements
- Hands on Technical lead with SoC & Netlist level DFT execution experience and one can guide juniors
- Scan Insertion: Stitching every flop in the design into shift registers (scan chains) to set the chip to any state and observe any state.
- ATPG (Automatic Test Pattern Generation): Running tools to generate patterns that detect manufacturing defects via the scan chains.
- MBIST (Memory BIST): Inserting on-chip memory test logic to allow RAMs and ROMs to self-test in the field.
- Boundary Scan and JTAG: Utilizing boundary scan and JTAG techniques for testing.
- Collaboration: Working closely with design and verification teams to optimize for test efficiency and fault isolation.
- Integration: Integrating test structures within the design of electronic components to facilitate efficient testing throughout the product lifecycle
More Info
Key Skills
About Company
Skills:
Gate Level Simulations, silicon debug, ATE Bring Up, Tessent MBIST, MBIST, NoTiming, Dft, Scan Insertion, ATPG, Tessent EDT, GLS Pattern Generation, Genus FC Scan Insertion, Timing, OCC SSN ATPG
Skills:
Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress
Skills:
Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC Coverage debug, Scan Insertion