Gate Level Simulations, silicon debug, ATE Bring Up, Tessent MBIST, MBIST, NoTiming, Dft, Scan Insertion, ATPG, Tessent EDT, GLS Pattern Generation, Genus FC Scan Insertion, Timing, OCC SSN ATPG

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC Coverage debug, Scan Insertion