We are looking for an experienced DFT Engineer with strong expertise in full-chip DFT implementation, ATPG, JTAG, and scan architecture. The ideal candidate must have hands-on experience with industry-standard DFT tools and should be capable of handling tasks independently.
Key Responsibilities:
- Execute full-chip DFT implementation & verification.
- Perform Scan Insertion, JTAG implementation, ATPG pattern generation, ATPG DRC, and coverage analysis.
- Use tools like Tessent, Synopsys, Cadence, and Spyglass DRC for DFT flows.
- Conduct timing/SDF-based pattern simulation debug and improve coverage metrics.
- Contribute to Silicon Debug, failure diagnostics, and root-cause analysis.
- Work closely with cross-functional teams to resolve design and simulation issues.
- Ensure efficient workflow with minimal supervision and strong communication.
Required Skills:
- 613 years of experience in DFT implementation & verification
- Strong knowledge of Verilog RTL, Scan Insertion, JTAG, ATPG
- Experience with Tessent DFT, Synopsys, or Cadence tools
- Proficiency in Spyglass DRC, coverage improvement, SDF-based debugging
- Good communication, analytical thinking & independent problem-solving
- Team player with adaptability to new challenges
How to Apply:
Interested candidates can apply by sharing their updated resume.
