DFT Engineer

Quess Corp

6-9 Years

Not Disclosed

Bengaluru, India

Posted 2 hours ago
Be among the first 10 applicants

Job Description

We are Hiring | DFT Engineer (3025) | 6–9 Years of Experience

We are hiring experienced DFT Engineers for an exciting opportunity with a leading Semiconductor MNC!

Experience: 6–9 Years

Primary Skill: DFT – Scan/ATPG

Interview Mode: Virtual / In-person

Key Skills & Responsibilities

DFT – Scan/ATPG

Strong experience in Scan/ATPG, DRC, and test coverage analysis.
Hands-on experience with Tessent tools, SSN/EDT, and scan pattern generation.
Knowledge of Stuck-at, Transition, Cell-Aware, and AFM fault models.
Experience in scan pattern simulation, debug, and coverage analysis.

DFX Design Verification

Experience in DFX DV for IP, debug units, clock/analog observe, PLL, RO, and thermal sensors.
Knowledge of JTAG networks, Boundary Scan, TDR verification, and clock-stop features.
Strong verification fundamentals, test-case development, coverage analysis, debugging, and root-cause analysis.

Good to Have

Experience with AMD flows and methodologies.
Strong scripting, analytical, and problem-solving skills.
Ability to work independently, take ownership, and collaborate effectively with cross-functional teams.

Important: Candidates should have strong hands-on expertise in at least one of the two key areas: DFT Scan/ATPG or DFX Design Verification. Scan/ATPG expertise is preferred.

Interested candidates, please share your updated resume via DM or apply through the relevant job link.

#Hiring #DFT #ScanATPG #SemiconductorJobs #VLSI #Tessent #DesignForTest #DFX #Verification #ASICDesign #EngineeringJobs

More Info

Job Type:

Industry:

Function:

Employment Type:

Key Skills

Tessent tools

coverage analysis

DFT – Scan ATPG

Debug

thermal sensors

SSN EDT

JTAG networks

DFX DV for IP debug units

TDR verification

clock-stop features

boundary scan

scan pattern generation

Pll

test-case development

clock analog observe

AFM fault models

scan pattern simulation

root-cause analysis

Debugging

About Company

Last Updated: 29-10-2026 05:21:44 PM

9-12 yrs

Bengaluru, India

Skills:

boundary scan , Debugging, Tessent tools, coverage analysis, clock analog observe PLL RO, DFT – Scan ATPG, thermal sensors, SSN EDT, JTAG networks, DFX DV for IP debug units, TDR verification, clock-stop features, scan pattern generation, test-case development, AFM fault models, scan pattern simulation, root-cause analysis

8-10 yrs

Bengaluru, India

Skills:

boundary scan , Perforce, Jtag, Git, Perl, Tcl, Verilog Hdl, Synopsys SMS SHS flow, Scan DRC flows, Mentor, Cadence, Siemens Tessent, AT-Speed SCAN, Dft, ATE silicon debug, EDA Tools, IJTAG, Multimedia subsystems DFT, MBIST, Shell flow, IO BIST, ATPG, Stuck-AT, Synopsys

4-10 yrs

Bengaluru, India

Skills:

test case generation , perl, Vcs, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, Tessent MBIST, TMBIST tool, NCSim, ATPG Coverage Improvement, Debugging Simulation Mismatches, MBIST Implementation, Tessent, Stuck-AT At-Speed Pattern Generation, Scan DRC fixing, TetraMax Tool, BISR, Modelsim, ATPG MBIST TestBench Validation, Scan Insertion

7-9 yrs

Bengaluru, India

Skills:

Gate Level Simulations, stuck-at transition, Scan Insertion, memory repair solutions, MBIST, JTAG boundary scan, bridge path delay, DFT architecture, EDA Tools, DRC, IEEE 1149.1, ATPG pattern generation, scan chain stitching, DFT rule checks

2-8 yrs

Bengaluru, India

Skills:

boundary scan , Perl, Python, Sta, Scan Insertion, SDC constraints, MBIST, Physical design flows, Verification, Rtl Design, SpyGlass DFT rules, Synthesis, JTAG protocols, ATPG pattern generation, Hierarchical DFT

DFT Engineer

Job Description

More Info

Key Skills

About Company

Similar Jobs