MBIST, ATPG, Dft, Scan Insertion, Siemens Tessent, DFT Simulation

boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis

Sed, Jtag, Awk, Tcl, Dft, Tessent, ATPG, Scan, MBIST, LBIST, Spyglass-DFT

bist , boundary scan , Jtag, test compression, ATPG, EDA Tools, Scan Insertion, DFT methodologies, Logic Memory, Synopsys TestMAX, Mentor Tessent

MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools

scan patterns generation, SSN OCC TAP verification, multi die DFT, Post silicon debug, ICL simulations, ATPG, scan-stitching, Tessent ATPG, timing and no-timing simulations, Pattern retargeting

Perl, Python, Logic Design, DFT Engineering, Uvm, Architecture Verification, Testplan Development, IOBIST Test-logic, Industry-standard Verification Flows, Constrained Random Testing, Automation Flow Development, Profiling Tools, Pre-Silicon Simulation and Debug, Coverage Metrics