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DFT Engineer

5-10 Years
15 - 30 LPA
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Job Description

Job Summary

We are looking for an experienced DFT Engineer with strong expertise in Design-for-Test (DFT) implementation, verification, and debug for complex SoC designs. The ideal candidate will be responsible for implementing, validating, and supporting DFT solutions using Mentor Tessent tools while working closely with Design, Verification, Physical Design, and Silicon Validation teams to ensure high-quality and testable silicon.

Key Responsibilities

  • Analyze design requirements and develop DFT solutions aligned with project objectives.
  • Perform DFT RTL insertion, DRC checks, verification, and debug using Mentor Tessent tools.
  • Implement and support Scan Insertion, Test Compression, ATPG, MBIST, JTAG, and IJTAG methodologies.
  • Generate, validate, and debug ATPG and MBIST patterns to achieve required test coverage.
  • Perform Gate-Level Simulation (GLS), including zero-delay and timing-enabled simulations.
  • Execute LBIST insertion and verification activities.
  • Collaborate with cross-functional teams to ensure successful DFT implementation and sign-off.
  • Analyze test coverage, identify gaps, and recommend improvements to enhance product quality.
  • Support silicon bring-up, failure analysis, production testing, and debug activities.
  • Create and maintain DFT documentation, test plans, and implementation guidelines.

Required Skills

  • 5+ years of hands-on experience in DFT implementation, verification, and debug.
  • Strong expertise in Mentor Tessent TestCompress/TestKompress.
  • Experience with Tessent DFT RTL insertion, Scan Insertion, ATPG, MBIST, and JTAG flows.
  • Hands-on experience in Mentor Tessent LBIST insertion and verification.
  • Strong experience with Cadence NCSim/Xcelium for timing and zero-delay DFT verification.
  • Good understanding of JTAG, Boundary Scan, IEEE 1500, and IJTAG (IEEE 1687) standards.
  • Experience with Gate-Level Simulation (GLS), SDF simulations, and timing analysis.
  • Working knowledge of Cadence Genus and LEC.
  • Familiarity with SpyGlass DFT and TCL scripting is an added advantage.
  • Strong Verilog debugging, analytical, troubleshooting, and problem-solving skills.
  • Excellent communication and collaboration abilities.

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Job ID: 149046227

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