
Search by job, company or skills
We are looking for an experienced DFT Engineer with strong expertise in Design-for-Test (DFT) implementation, verification, and debug for complex SoC designs. The ideal candidate will be responsible for implementing, validating, and supporting DFT solutions using Mentor Tessent tools while working closely with Design, Verification, Physical Design, and Silicon Validation teams to ensure high-quality and testable silicon.
Job ID: 149046227
Skills:
logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, Post Silicon debug analysis, Pattern simulation, DFT architectures, Chip level DFT, ATPG Pattern generation, JTAG BSDL, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, stuck at IDDQ, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, scan patterns and coverage statistics
Skills:
bist , simulation and verification flow, Scan Insertion, DFT specification definition, compressed ATPG patterns, debug and validation of DFT features, analog mixed-signal IPs, silicon bring-up, gate level simulations, ASIC DFT synthesis, low power designs, IJTAG tools and flow
Skills:
boundary scan , Scripting, Jtag, Perl, Tcl, Scan Insertion, Yield analysis, DFT methodologies, MBIST, Debugging silicon test issues, ATPG, Programming using Python
Skills:
Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, Tessent, JTAG protocols, ATPG, Gate level simulation, TestMax
Skills:
Static Timing analysis, Boundary Scan inserting tap controller, generating TDL for ATE, DFT simulation with and without SDF, analysing and improving scan coverage, P1500, Synthesis and formal verification tools, RTL based and netlist-based insertion flows, Stuck-At and At-Speed Faults, Inserting Scan and generating ATPG vectors, characterization DC Characteristics, DFT tools from Mentor, MBIST insertion and simulation
We don’t charge any money for job offers