DFT Engineer

We are looking for a highly skilled DFT Engineer with strong hands-on experience in scan insertion, ATPG, and advanced DFT methodologies. The ideal candidate will drive DFT implementation across complex SoCs, work closely with RTL and Physical Design teams, and ensure high-quality, testable designs meeting coverage and silicon quality goals.

Key Responsibilities

• Lead and execute Design-for-Testability (DFT) implementation for complex SoC designs.
• Perform Scan Insertion, ATPG, ICL, and SSN activities across different project phases.
• Develop and integrate Scan Chains, Boundary Scan, and BIST architectures.
• Use industry-standard tools such as Synopsys DFT Compiler, Test Kompress, and Xelium for DFT insertion and validation.
• Generate, analyze, and optimize ATPG patterns for high fault coverage.
• Perform Pattern Retargeting, handle DFT DRC violations, and drive coverage improvement initiatives.
• Review and sign off DFT deliverables, ensuring compliance with quality and schedule requirements.

Mandatory Skills & Experience

• 4+ years of hands-on experience in DFT Engineering with a strong focus on Scan Insertion and ATPG.
• Strong expertise in DFT methodologies including:
• Scan Chains
• ATPG
• Boundary Scan
• BIST
• Proven experience using Synopsys DFT tools:
• DFT Compiler
• Test Kompress
• Xelium
• Hands-on experience in:

Pattern Retargeting

DFT DRC Debugging and Resolution

Coverage analysis and improvement

Good-to-Have Skills

• Experience working on advanced technology nodes and large SoC designs.
• Knowledge of low-power DFT techniques and test compression methodologies.
• Exposure to silicon bring-up and post-silicon debug is a plus.