DFT Engineer
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Job Description for DFT Engineer
Required Skills:
4 to 6 years of experience
Location Bangalore
-Experience in Scan insertion with compression for Stuck-At and At-Speed test.
-Experience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debug.
-Experience in MBIST insertion, simulation and debug on RTL and gates netlist
-Experience in Boundary Scan insertion, simulation and verification.
-Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys).
Job ID: 152380553
Skills:
Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Mentor, Cadence, TetraMax, Gate level simulations, Synthesis, AMBA, ATPG, Digital RTL coding, Timing Constraints, Synopsys, PMIC
Skills:
Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan
Skills:
Perl Shell Scripting, Scan Insertion, Production enablement, Stuck at Transition ATPG, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning
Skills:
Timing Analysis, DFT insertion flows, IEEE1500, Debug and Analysis of failures, equivalency checks, IEEE1687, JTAG 1149.1, SoC ASIC Digital Design, Cadence tools and flows, Verification of ATPG testbenches, scan chain insertion, LBIST, compression scan insertion
Skills:
Verilog, Scan Insertion, Synopsys, DFT tools, systemverilog, Mentor Siemens Tessent, ATPG, Gate-Level Simulation, Cadence
