Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Mentor, Cadence, TetraMax, Gate level simulations, Synthesis, AMBA, ATPG, Digital RTL coding, Timing Constraints, Synopsys, PMIC

Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan

Perl Shell Scripting, Scan Insertion, Production enablement, Stuck at Transition ATPG, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning

Timing Analysis, DFT insertion flows, IEEE1500, Debug and Analysis of failures, equivalency checks, IEEE1687, JTAG 1149.1, SoC ASIC Digital Design, Cadence tools and flows, Verification of ATPG testbenches, scan chain insertion, LBIST, compression scan insertion

Verilog, Scan Insertion, Synopsys, DFT tools, systemverilog, Mentor Siemens Tessent, ATPG, Gate-Level Simulation, Cadence

Jtag, MBIST, FastScan, Scan Insertion, DFT architecture, ATPG, Synopsys TetraMax, EDT, Scan Compression, Stuck-at, At-speed, TestKompress, Mentor Tessent

IEEE1500, DFT insertion flows, Timing Analysis, equivalency checks, IEEE1687, Debug and Analysis of failures, JTAG 1149.1, SoC ASIC Digital Design, Cadence tools and flows, Verification of ATPG testbenches, scan chain insertion, LBIST, compression scan insertion