Senior DFT Engineer

Company Description BigEndian Semiconductors is a fabless semiconductor startup building secure, high-performance SoCs in India for global markets, targeting surveillance, telecom, IoT, and enterprise systems. Founded by a seasoned team with experience in 4G chipsets and unicorn-scale SaaS platforms, the company emphasizes a security by design approach that tightly integrates hardware and software. Leveraging deep expertise in VLSI, system architecture, and embedded software, BigEndian is creating trusted silicon solutions for both national security and commercial applications. Headquartered in Bengaluru, with strategic partnerships in Taiwan and India and backing from leading industry veterans, government programs, and deep-tech investors, BigEndian is contributing to India's emergence as a global hub for semiconductor design and innovation.
Role Description This is a full-time, on-site Senior DFT Engineer role based in Bengaluru. The Senior DFT Engineer will architect and implement Design-for-Test (DFT) strategies for complex SoCs, including scan insertion, MBIST, LBIST, and boundary scan to achieve high test coverage and quality. Day-to-day responsibilities include developing and validating test architectures, generating and optimizing test patterns, collaborating with front-end and back-end design teams, and supporting bring-up and debug on silicon in the lab. The role involves analyzing test results, driving yield and coverage improvements, working closely with test engineering and manufacturing partners, and contributing to DFT methodology, flows, and automation across projects. The Senior DFT Engineer will also mentor junior engineers and help define best practices for secure and reliable silicon platforms.
Qualifications

• Candidates should possess strong skills in Test Engineering, including developing robust DFT architectures and methodologies.
• Candidates should possess experience in Test Execution, including executing and validating test plans and test programs on simulation and silicon.
• Candidates should possess the ability to design and manage effective Test Cases, including pattern generation, optimization, and coverage analysis.
• Candidates should possess expertise in Testing and Functional Testing, including debugging failures, analyzing logs, and improving test quality and yield.
• Solid understanding of digital design, RTL, synthesis, static timing analysis, and SoC architecture.
• Hands-on experience with scan, MBIST/LBIST, ATPG tools (e.g., Tessent, Synopsys, Cadence) and industry-standard EDA flows.
• Experience with silicon bring-up, lab equipment, and collaboration with ATE/test house teams is highly beneficial.
• Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field, with several years of relevant DFT experience in complex SoCs.
• Strong problem-solving, communication, and collaboration skills, with the