boundary scan , Test Engineering, static timing analysis, Soc Architecture, Functional Testing, Test Execution, Testing, coverage analysis, lab equipment, debugging failures, Scan Insertion, EDA flows, MBIST, Cadence, Digital Design, Tessent, RTL synthesis, silicon bring-up, test architectures, test patterns, pattern generation, LBIST, Synopsys, ATPG tools

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC

boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, Timing Analysis, MBIST, DFT methodologies, Siemens Tessent, circuit fundamentals, compressed scan, IEEE 1500, IEEE 1687, ATPG coverage analysis, Cadence Modus, Genus, SDF-based simulations

memory test , Digital Logic Design, static timing analysis, Hdl, Gate level scan insertion, test clocking, Scan ATPG compression techniques, ASIC Logic Design Flow, Scan ATPG, JTAG IEEE1149.1, DFT methodologies, Rtl Design, DFT architecture verification, security mechanisms, BIST architecture, ATPG configurations, post-silicon validation, Eco, JTAG boundary scan