Soc Architecture, Tcl, Python, Perl, HDLs, MBIST, ATPG flow implementation, UPF, Cadence digital implementation tools, DFT architecture definition, Tempus, CPF, Scan, Genus, tessent DFT, JTAG boundary scan

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC Coverage debug, Scan Insertion

Jtag, Perl, Verilog, Python, Tcl, Scan Insertion, Cadence DFT EDA tools, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT implementation and verification, DFT rule checking, ATPG, scan chain stitching, Boundary Scan BSCAN

memory test , Digital Logic Design, static timing analysis, Hdl, Gate level scan insertion, test clocking, Scan ATPG compression techniques, ASIC Logic Design Flow, Scan ATPG, JTAG IEEE1149.1, DFT methodologies, Rtl Design, DFT architecture verification, security mechanisms, BIST architecture, ATPG configurations, post-silicon validation, Eco, JTAG boundary scan

Built-In Self-Test (BIST), Test Methodologies, Scan chains