DFT Engineer
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Key Responsibilities:
- Interface with ASIC design teams to ensure DFT design rules and coverages are met.
- Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.
- MBIST verification (including repair), test pattern generation through Mentor tool.
- ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
- Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
- Responsible for supporting post-silicon debug effort, issue resolution.
- Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.
- Developing, enhancing and maintaining scripts as necessary.
Preferred Experience:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering
- 7 to 15 years experience in ASIC/DFT - simulation and Silicon validation.
- Should have worked in at least one Full chip DFT
- Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement.
- In-depth knowledge and hands-on experience in ATPG - coverage analysis.
- In-depth knowledge of Memory verification, repair and failure root-cause analysis.
- Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim.
- Expertise in scripting languages such as Perl, shell, etc. is an added advantage.
- Ability to work in an international team, dynamic environment with good communication skills.
- Ability to learn and adapt to new tools, methodologies.
- Ability to do multi-tasking & work on several high-priority designs in parallel.
More Info
About Company
Skills:
Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification
Skills:
Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, silicon debug, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Synopsys Tetramax, SOC Tape-Outs, Verilog RTL design, DFTMAX, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax
Skills:
Jtag, Dft, ATPG, Scan Insertion
Early Applicant
Skills:
MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools