Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification

Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, silicon debug, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Synopsys Tetramax, SOC Tape-Outs, Verilog RTL design, DFTMAX, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax

Jtag, Dft, ATPG, Scan Insertion

MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools

boundary scan , Jtag, Perl, Shell scripting, Python, Tcl, Scan Insertion, MBIST, SMS and SEQ insertion, Multi-clock DFT architectures, Scan compression, Test clocks, Transition fault pattern generation, ATPG, Resets, DFT DRC debugging, Synopsys DFT tools, Coverage closure

boundary scan , DFT Engineer, Design For Test, Dfm, DFT Methodology, DFT Flows, Scan Insertion, ATPG, MBIST, Scan Compression, DFT Verification, DFT Implementation, DFT Architecture, DFT Pattern Generation, Design For Testability

scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis