Logic Design, Sta, scan BIST, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

Silicon Validation, DDR, Sta, RTL Synthesis, P R Verification, SERDES, ASIC SOC design, MBIST, DFT methodologies, Mixed Signal IPs, Pll, Dft, ATPG, EDA Tools, Scan, manufacturing test flows

logic bist , Usb, Perl, Pcie, Shell scripting, Static Timing Analysis, Python, Tcl, Memory BIST, Mentor, Cadence, IEEE 1149.1 JTAG, IEEE 1500, Analog Mixed-Signal test structures, DFT architecture, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

bist , Jtag, ATPG, Cadence Modus, Synopsys DFTMAX, Scan Insertion, DFT methodologies, Mentor Tessent

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

DFT verification, MBIST insertion, EDA Tools, Fault Simulation, Pattern generation

DFT insertion flows, JTAG 1149.1, IEEE1687, IEEE1500, Cadence tools and flows, SoC ASIC Digital Design, Timing Analysis, Verification of ATPG testbenches, Debug and Analysis of failures, LBIST, scan chain insertion, compression scan insertion, equivalency checks

Tcl, Python, Perl, Scan Architecture, Gate-level Simulation, MBIST, Scan Insertion, ATPG, Scan Compression, DFT Validation, IEEE 1500 standards

Vcs, Scan Insertion, ATE patterns, JTAG protocols, ATPG, Post-silicon validation, Tessent tool sets, P1687, TestMax, TetraMax, Gate level simulation debugging