DFT Engineer

Experience

5+ years of hands‑on experience in Design‑for‑Test (DFT) for ASIC / SoC designs.

Scope of Work

Implement and support DFT architectures for digital / mixed‑signal SoCs, including:

Scan (full/partial), scan compression

MBIST / LBIST

JTAG/IJTAG / boundary scan

Execute DFT RTL insertion, integration, and verification in collaboration with RTL, PD, and DV teams.

Review and influence clocking, reset, and low‑power intent from a DFT perspective.

Run DFT tool flows and support DFT sign‑off (coverage, rule checks, readiness for ATPG).

Debug DFT issues across RTL, synthesis, and gate‑level netlists.

Support test engineering handoff, pattern readiness, and post‑silicon debug as needed.

Maintain DFT specs, checklists, and documentation; capture lessons learned.

Required Skills

Strong fundamentals in digital design (clocks, resets, timing, FSMs).

Solid experience with:

Scan insertion and coverage analysis

MBIST/LBIST architectures

Test modes and DFT verification

Hands‑on with industry DFT tools (one or more):

Siemens Tessent, Synopsys DFT Compiler, or equivalent

Proficiency in Verilog / SystemVerilog.

Ability to work independently on assigned DFT blocks or subsystems.

Good‑to‑Have

Experience with mixed‑signal / PMIC / memory‑interface SoCs.

Exposure to post‑silicon debug or yield‑related DFT issues.

Tcl / Python scripting for flow automation.

Prior experience working as vendor/EWF in large semiconductor programs.