DFT Engineer
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Job Description
Description
We are seeking an experienced DFT Engineer to join our team in India. The ideal candidate will have a strong background in design for test methodologies and be responsible for ensuring that our digital designs are testable and meet quality standards.
Responsibilities
- Develop and implement DFT (Design for Test) strategies for complex digital designs.
- Work closely with design teams to ensure testability is integrated into the design process.
- Create and maintain DFT documentation, including test plans and reports.
- Perform DFT simulations and analyze results to improve design quality and test coverage.
- Collaborate with manufacturing and test engineering teams to ensure efficient DFT implementation.
- Debug and resolve issues related to DFT during the design and production phases.
Skills and Qualifications
- 7-9 years of experience in DFT methodologies and tools.
- Proficient in using DFT tools such as Synopsys DFT Compiler and Mentor Graphics Tessent.
- Strong understanding of digital design principles and RTL coding (Verilog/VHDL).
- Experience in scan insertion, boundary scan, and JTAG standards.
- Familiarity with test coverage analysis and fault simulation.
- Ability to work collaboratively in a team environment and communicate effectively with cross-functional teams.
More Info
Key Skills
DFT Techniques
DFT Tooling
Debugging Skills
About Company
Skills:
Static timing analysis, ATPG tools, Scripting skills, DFT Architecture
Skills:
Timing Analysis, DFT insertion flows, IEEE1500, Debug and Analysis of failures, equivalency checks, IEEE1687, JTAG 1149.1, SoC ASIC Digital Design, Cadence tools and flows, Verification of ATPG testbenches, scan chain insertion, LBIST, compression scan insertion
Skills:
Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up
Skills:
Verilog, Scan Insertion, Synopsys, DFT tools, systemverilog, Mentor Siemens Tessent, ATPG, Gate-Level Simulation, Cadence
Skills:
Tempus, HDLs, MBIST, DFT architecture definition, ATPG flow implementation, JTAG boundary scan insertion, Pattern Simulation, Scan, Genus, Cadence digital implementation tools