Static timing analysis, ATPG tools, Scripting skills, DFT Architecture

Timing Analysis, DFT insertion flows, IEEE1500, Debug and Analysis of failures, equivalency checks, IEEE1687, JTAG 1149.1, SoC ASIC Digital Design, Cadence tools and flows, Verification of ATPG testbenches, scan chain insertion, LBIST, compression scan insertion

Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up

Verilog, Scan Insertion, Synopsys, DFT tools, systemverilog, Mentor Siemens Tessent, ATPG, Gate-Level Simulation, Cadence

Tempus, HDLs, MBIST, DFT architecture definition, ATPG flow implementation, JTAG boundary scan insertion, Pattern Simulation, Scan, Genus, Cadence digital implementation tools

Vcs, ATE patterns, Scan Insertion, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax

boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis