DFT Engineer
DFT Engineer
cadence- Posted 2 hours ago
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Job Description
Job Overview:
Be a part of the Modus PE team in identifying new features in DFT & ATPG domains and developing product spec for implementation. Work with R&D & PV teams with validation of said features, Development of methodologies, flows and documentation to help improve usability and quality of the tool. Collaborate with field to benchmark on customer designs towards successful deployment.
Skills and Experience Requirements:
- 2- 7 Years of experience in DFT & ATPG with strong technical background and extensive experience in DFT methodologies.
- Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies.
Education: B. Tech/ B.E / M.E. M Tech in ECE/VLSI/ Electrical or related filed
Behavioral skills required:
- Must possess strong written, verbal and presentation skills.
- Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
- Ability to establish a close working relationship with both customer peers and management.
- Explore what's possible to get the job done, including creative use of unconventional solutions
- Work effectively across functions and geographies
- Push to raise the bar while always operating with integrity
More Info
Key Skills
DFT techniques
DFT methodologies
About Company
Skills:
Built-In Self-Test (BIST) implementation, Design for Testability (DFT), boundary scan standards, scan chain insertion and optimization techniques, silicon debug and failure analysis processes
Skills:
Scan Compression Techniques, Fault Models, DFT Tools, Sign-Off, Scripting Automation, DFT Implementation, Boundary Scan IEEE 1149.1, Test Coverage Optimization, Post-Silicon Validation
Skills:
boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis
Skills:
boundary scan , bist , Jtag, Mentor Tessent, Synopsys TestMAX, EDA Tools, ATPG, Logic Memory, test compression, DFT methodologies, Scan Insertion
Skills:
Logic Built-In Self-Test (LBIST), Automatic Test Pattern Generation (ATPG), ATPG tools (Mentor TK), Static timing analysis, Timing Closure, Debug skills, On-chip test compression techniques, Scripting skills, Structural DFT, DFT Architecture and Design