Job Title: DFT Engineer
Location: Bangalore, India
Experience: 5+ Years
Open Positions: 5
Education: Bachelor's Degree in Electrical Engineering / Electronics Engineering or related field
Work Mode: Onsite
Job Summary
The DFT Engineer will be responsible for implementing and validating Design-for-Test (DFT) methodologies for complex SoC designs. The role includes scan architecture implementation, ATPG generation, MBIST integration, and gate-level simulation validation to ensure high manufacturing test coverage. The engineer will work closely with RTL, physical design, and verification teams to enable robust test strategies across the chip design lifecycle.
Key Responsibilities
DFT Architecture & Implementation
- Define and implement DFT strategies including scan insertion, test compression, and memory BIST integration for complex SoC designs.
- Develop and maintain DFT architecture aligned with product testability and coverage requirements.
- Integrate scan chains, test modes, and test control logic into RTL/netlist.
ATPG & Test Pattern Development
- Generate ATPG patterns for stuck-at, transition, and other fault models.
- Analyze and improve fault coverage using industry standard ATPG tools.
- Debug pattern generation issues and optimize test coverage and test time.
Memory BIST Integration
- Implement and verify MBIST solutions for embedded memories.
- Configure memory test controllers and integrate with SoC test infrastructure.
- Support memory repair and redundancy implementation when required.
Verification & Validation
- Perform Gate Level Simulation (GLS) for test validation.
- Validate scan chains, test patterns, and test modes.
- Debug DFT issues during pre-silicon validation.
DFT Sign-off & Quality
- Perform linting and structural checks using SpyGlass or equivalent tools.
- Ensure DFT design meets test coverage and quality targets.
- Work closely with physical design teams for DFT-related constraints.
Cross-Functional Collaboration
- Coordinate with RTL, verification, and physical design teams during implementation.
- Support silicon bring-up and manufacturing test activities.
Required Technical Skills
Core DFT Expertise
- Hands-on experience with Scan Insertion and Scan Architecture
- Experience in ATPG pattern generation and fault coverage analysis
- Strong knowledge of MBIST architecture and memory testing
Tools & Methodologies
- Experience with SpyGlass for lint and DFT structural checks
- Hands-on experience with ATPG tools (Tessent / TetraMAX / Modus or similar)
- Experience with Gate Level Simulation (GLS) for DFT validation
SoC & Digital Design Understanding
- Good understanding of digital design and RTL concepts
- Experience working on SoC level DFT implementation
- Understanding of test compression techniques
Debug & Validation
- Strong debugging skills for scan chain failures and pattern issues
- Experience with DFT verification and silicon test readiness
Tools & Technologies
- SpyGlass
- ATPG Tools (Tessent / TetraMAX / Modus or equivalent)
- DFT Flow Tools
- Simulation Tools for GLS
- RTL and SoC design environments
Education
Bachelor's Degree in Electrical Engineering / Electronics Engineering or equivalent.
