DFT Engineer
DFT Engineer
AMD Ventures- Posted 2 months ago
- Be among the first 10 applicants
Job Description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
MTS SILICON DESIGN ENGINEER
As key member of the AMD EPYC Server team, the successful candidate will play a significant role in ensuring the quality of next generation EPYC Server SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques.
Primary Responsibilities Will Include
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.
This posting is for an existing vacancy.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
MTS SILICON DESIGN ENGINEER
As key member of the AMD EPYC Server team, the successful candidate will play a significant role in ensuring the quality of next generation EPYC Server SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques.
Primary Responsibilities Will Include
- Working closely with the Architecture team to understand the DFT Architecture and implementation
- Interfacing with the Design teams to ensure DFT design rules and guidelines are met
- Working with the PD team to ensure to correct DFT implementation and closing timing
- Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques.
- Simulating and verifying the ATPG and LBIST patterns
- Analyzing and working with the different stakeholders to get the required design changes in to get the maximum ATPG coverage
- Working with the Product engineering teams on the delivery of manufacturing test patterns.
- Working with the Product Engineering teams on Silicon bring-up and debugs
- Developing, enhancing and maintaining scripts as necessary
- Exposure to DFT Architecture and Design
- Good working knowledge of ATPG tools (Mentor TK)
- Exposure to Static timing analysis & Timing closure is required.
- Excellent hands-on debug skills and scripting skills are critical.
- Must have good communication skills and the ability to work in a worldwide team environment.
- B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 9+ years of DFT experience
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.
This posting is for an existing vacancy.
More Info
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Key Skills
Scripting skills
Debug skills
Logic Built-In Self-Test (LBIST)
On-chip test compression techniques
Automatic Test Pattern Generation (ATPG)
ATPG tools (Mentor TK)
Structural DFT
DFT Architecture and Design
About Company
Skills:
Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, silicon debug, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Synopsys Tetramax, SOC Tape-Outs, Verilog RTL design, DFTMAX, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
Pre-silicon DFT verification, Post-silicon validation, Yield improvement, BSCAN, Hierarchical multi-core test strategies, MBIST, Scripting and automation, Scan compression, GLS, Power-aware DFT, ATPG simulation, ATPG, Debug, DFT timing closure, LBIST, ATE test program development, Coverage closure, IJTAG, Silicon bring-up
Skills:
Perl Shell Scripting, Scan Insertion, Stuck at Transition ATPG, Production enablement, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
Vcs, Perl, Python, Tcl, ATPG Fault Models, DFT Debugging, Siemens Tessent, Synopsys TestMAX, End-to-end DFT implementation, RTL SoC Design Flow, Cadence Modus, STA Timing Closure, MBIST LBIST, DFT Sign-off Fault Coverage, JTAG Boundary Scan – IEEE 1149.1, Scan Insertion Compression
Skills:
Scan insertion and compression, DFT architecture planning, Boundary scan IEEE 1149.1 1149.6 IJTAG 1687, MBIST, Fault grading, ATPG pattern generation, Logic BIST insertion and validation, Synthesis flows, Rtl Design, Sta