Logic Built-In Self-Test (LBIST), Automatic Test Pattern Generation (ATPG), ATPG tools (Mentor TK), Static timing analysis, Timing Closure, Debug skills, On-chip test compression techniques, Scripting skills, Structural DFT, DFT Architecture and Design

Pre-silicon DFT verification, Post-silicon validation, Yield improvement, BSCAN, Hierarchical multi-core test strategies, MBIST, Scripting and automation, Scan compression, GLS, Power-aware DFT, ATPG simulation, ATPG, Debug, DFT timing closure, LBIST, ATE test program development, Coverage closure, IJTAG, Silicon bring-up

Perl Shell Scripting, Scan Insertion, Stuck at Transition ATPG, Production enablement, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

Vcs, Perl, Python, Tcl, ATPG Fault Models, DFT Debugging, Siemens Tessent, Synopsys TestMAX, End-to-end DFT implementation, RTL SoC Design Flow, Cadence Modus, STA Timing Closure, MBIST LBIST, DFT Sign-off Fault Coverage, JTAG Boundary Scan – IEEE 1149.1, Scan Insertion Compression

Scan insertion and compression, DFT architecture planning, Boundary scan IEEE 1149.1 1149.6 IJTAG 1687, MBIST, Fault grading, ATPG pattern generation, Logic BIST insertion and validation, Synthesis flows, Rtl Design, Sta

Perl, Shell scripting, Scan Insertion, Stuck at Transition ATPG, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning, silicon debug, Synopsys Tetramax, SOC Tape-Outs, DFTMAX