Usb, Pcie, Perl, Shell scripting, Python, Tcl, Cadence, Mentor, IEEE 1149.1 JTAG, IEEE 1500, DFT architecture, Analog Mixed-Signal test structures, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

Perl Shell Scripting, Stuck at Transition ATPG, Production enablement, Scan Insertion, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

Silicon Validation, DDR, Sta, RTL Synthesis, ASIC SoC design DFT methodologies, P R Verification, SERDES, Mixed Signal IPs, MBIST, Pll, Dft, ATPG, EDA Tools, Scan, manufacturing test flows

DFT architecture, EDA Tools, Fault Simulation, DFT verification plans, MBIST, Pattern generation

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

Logic Design, pattern generation, Fault Simulation, automation methods, Fault Models, VLSI simulation tools, tessent, ATPG, gate level simulation, Sta, on-chip scan compression, scan BIST

DFT insertion flows, JTAG 1149.1, IEEE1687, IEEE1500, Cadence tools and flows, SoC ASIC Digital Design, Timing Analysis, Verification of ATPG testbenches, Debug and Analysis of failures, LBIST, scan chain insertion, compression scan insertion, equivalency checks

Tcl, Python, Perl, Scan Architecture, Gate-level Simulation, MBIST, Scan Insertion, ATPG, Scan Compression, DFT Validation, IEEE 1500 standards