DFT Design Engineer
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ROLE & RESPONSIBILITIES:
Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off.
Be responsible for a comprehensive DFT plan.
Incumbent to work with DFT and cross functional teams.
To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field.
ESSENTIAL SKILLS & EXPERIENCE:
Strong fundamentals on DFT and ASIC cycle.
Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player.
Hands-on experience with DFT implementation using standard EDA and flow is a must.
Job ID: 111840919
Skills:
simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities
Skills:
logic bist , static timing analysis, UNIX, Jtag, Linux, Perl, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, Verilog simulator, equivalency checking, ATPG, EDA Tools, scan compression architecture, SSN Scan, IEEE standards, c-shell
Skills:
Logic Design, Static Timing Analysis, Tcl, Python, Perl, Jasper, IR drop, coverage analysis, RTL lint tools, ATE debug, Logic Synthesis, EDA Tools, Sta, RTL2GDS flow, Logic Equivalent Checking, Cadence Modus, Synthesis, post silicon validation, Verification, DFT concepts, ATPG tools, RTL implementation, debugging skills, Scan Insertion
Skills:
boundary scan standards, scan chain insertion and optimization techniques
Skills:
logic bist , static timing analysis, UNIX, Jtag, Perl, Linux, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, Verilog simulator, equivalency checking, ATPG, EDA Tools, scan compression architecture, IEEE standards, SSN Scan, c-shell
