Design Verification Lead
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Key Responsibilities: Min 10+ years experience required.
Location: Hyderabad/Bangalore
Verification Architecture & Planning
Define and execute verification strategy for subsystems: o SPI, UART, I2C o Audio interfaces (I2S, TDM) o Power management digital controllers
Develop test plans with full functional and corner-case coverage
Identify verification risks and coverage gaps early
UVM-Based Verification Development
Build and maintain UVM/System Verilog testbenches Develop: o Reusable VIPs and monitors o Scoreboards and checkers o Constrained-random stimulus
Implement protocol-aware verification components
Coverage & Quality • Drive: o Functional coverage o Code coverage (line, toggle, FSM)
Ensure closure of: o Coverage goals o Assertion checks
Track and report verification metrics
Debug & Validation
Debug RTL issues and root-cause failures
Work closely with RTL engineers on bug fixes and improvements
Support post-silicon validation with test reuse where applicable
System-Level Verification
Contribute to SoC-level verification: o Subsystem integration scenarios o Firmware-driven tests • Validate interactions across clock, reset, and power domains
Required Qualifications
10+years of DV experience in SoC/subsystem verification
Strong expertise in: o System Verilog and UVM o Functional coverage and assertions (SVA) • Experience verifying: o AMBA protocols (AXI/AHB/APB) o Peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)
Preferred Qualifications
Experience with mixed-signal verification environments (AMS co-sim is a plus)
Exposure to low-power verification (UPF/CPF)
Familiarity with ARM Cortex-M33 or RISC-V SoCs
Job ID: 153919019
Skills:
Verification methodologies such as UVM, Understanding of StarRC Calibre parasitic extraction flow, NAND Flash memory design, Test Bench development in System Verilog
Skills:
C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog
Skills:
C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog
Skills:
C, coverage closure, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog
Skills:
System Verilog, Ovm, FPGA prototyping, Uvm, Pre Silicon Validation Verification, FPGA architecture, constrained random verification methodologies
