
Search by job, company or skills
Role Overview
This is a leadership role for a highly experienced Design Verification engineer who can drive end-to-end verification for a block, subsystem, or SoC. The ideal candidate combines deep hands-on expertise in SystemVerilog/UVM with strong technical leadership, a track record of mentoring teams, and the ability to deliver robust verification outcomes on complex semiconductor programs.
Core Responsibilities
Required Technical Experience
Preferred Skills
Location: Bangalore, Hyderabad, Kochi, Chennai
Company Description
Screen2Hire Consulting LLP is a leading DeepTech talent advisory specializing in Semiconductor, VLSI, Embedded Systems, AI-led engineering, and SpaceTech domains. The company supports fabless startups, semiconductor design services firms, and product engineering teams by building high-caliber talent pipelines for design-to-silicon and system validation lifecycles. With over 20 years of global recruitment leadership, Screen2Hire offers unparalleled expertise in scarce-skill hiring, long-term workforce planning, and talent intelligence. Based in India, the company focuses on helping organizations scale responsibly in the rapidly growing semiconductor and space innovation ecosystem.
Job ID: 147871467
Skills:
perl scripting, Jasper, Verilog, Computer Architecture, System Verilog, VSI-FV, digital systems, assembly x86 code, IEV, IFV, CPU verification, Formal Verification methodology
Skills:
Verification of IP designs, ASIC standard interfaces, Verification of AI ML Accelerators, Electrical Engineering, Memory system architecture, Functional coverage, systemverilog
Skills:
perl scripting, Jasper, Verilog, Computer Architecture, System Verilog, VSI-FV, digital systems, assembly x86 code, IEV, IFV, CPU verification, Formal Verification methodology
Skills:
C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, cache controllers, x86 assembly, semi randomized test generators, FPGA HW platforms, Uvm, systemverilog, Validation using Emulation, validation strategy development, memory coherency, debugging test failures, power management, coverage driven Validation methodologies
Skills:
perl, Pcie, Tcl, Axi, UCIe, Uvm, SV, CXL, CHI, Ace, standard VIP
We don’t charge any money for job offers