perl scripting, Jasper, Verilog, Computer Architecture, System Verilog, VSI-FV, digital systems, assembly x86 code, IEV, IFV, CPU verification, Formal Verification methodology

Verification of IP designs, ASIC standard interfaces, Verification of AI ML Accelerators, Electrical Engineering, Memory system architecture, Functional coverage, systemverilog

perl scripting, Jasper, Verilog, Computer Architecture, System Verilog, VSI-FV, digital systems, assembly x86 code, IEV, IFV, CPU verification, Formal Verification methodology

C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, cache controllers, x86 assembly, semi randomized test generators, FPGA HW platforms, Uvm, systemverilog, Validation using Emulation, validation strategy development, memory coherency, debugging test failures, power management, coverage driven Validation methodologies

perl, Pcie, Tcl, Axi, UCIe, Uvm, SV, CXL, CHI, Ace, standard VIP

System Verilog, Pcie, Protocol analyzers, Bring up tools, Uvm, Verification and validation flows, Oscilloscopes

Verification methodologies, Uvm, Functional Verification, systemverilog, SoC/IP verification

Python Scripting, System Verilog, SOC design, AXI Protocol, SoC Verification, UVM Testbench

Ovm, Pcie, Verilog, Ethernet, System Verilog, power management flows, Uvm, HSIO, Low Power Verification, RTL GLS level simulations, SOC bot flow, System Verilog Assertions