Job Title: DV Lead/Senior Engineer
Experience: 4+ Years
Location: Any
Employment Type: Full-Time
Key Responsibilities
- Develop and execute verification plans for high-speed interfaces including PCIe Gen3+, DDR4/5, Ethernet (10G+), MIPI, USB 3.0+, and related protocols like NVMe or UCIe.
- Create UVM testbenches with drivers, monitors, scoreboards, and coverage models; perform constraint-random and directed testing.
- Debug RTL simulations, analyze coverage closure, and support emulation/prototyping for silicon bring-up and post-silicon validation.
Required Qualifications
- Bachelor's/Master's in Electrical Engineering or related field with 4+ years in design verification for high-speed protocols.
- Strong proficiency in SystemVerilog, UVM, and scripting (Python/Perl); experience with tools like VCS, Questa, or Synopsys simulators.
- Familiarity with on-chip buses (AXI/APB/AHB), assertions, low-power verification (UPF/CPF), and protocol analyzers.
Preferred Skills
- Experience integrating third-party VIPs and working with AMBA protocols in SoC environments.
- Knowledge of board bring-up, silicon debug, or FPGA validation for protocols like JESD204 or SerDes.
- Excellent problem-solving and team collaboration skills for cross-functional projects.
