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Design verification
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Design verification
InfosysThis job is no longer accepting applications
Job Description
- Coverage driven verification using UVM - Strong System Verilog knowledge along with Assertion coding - Strong debugging skills - GLS, XProp and PA sims - Excellent problem-solving and analytical skills - Experience with verification methodologies and tools - Knowledge of scripting languages such as Perl or Python - Good communication and collaboration skills - Working experience on protocol like , AXI/PCIe/CXL/Ethernet/DMAC/USB/UFS - Good leadership skills.
- As part of the Infosys delivery team, your primary role would be to interface with the client for quality assurance, issue resolution and ensuring high customer satisfaction.
- You will understand requirements, create and review designs, validate the architecture and ensure high levels of service offerings to clients in the technology domain.
- You will participate in project estimation, provide inputs for solution delivery, conduct technical risk planning, perform code reviews and unit test plan reviews.
- You will lead and guide your teams towards developing optimized high quality code deliverables, continual knowledge management and adherence to the organizational guidelines and processes.
- You would be a key contributor to building efficient programs/ systems and if you think you fit right in to help our clients navigate their next in their digital transformation journey, this is the place for you! If you think you fit right in to help our clients navigate their next in their digital transformation journey, this is the place for you!
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Key Skills
About Company
Skills:
Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA
Skills:
Fpga, Vcs, Pcie, Ethernet, Xcelium, Emulation, Uvm, systemverilog, Dft, Questa, DDR5, DDR4
Skills:
Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus
Skills:
Perl, Ruby, System Verilog, Asic verification, Rtl Design, make, Uvm, formal verification, TestBench Development
Skills:
Test Planning, C, Systemc, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, formal verification, constrained-random verification, power-aware verification