code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, DDR4, Uvm, Functional coverage, Assertions, LPDDR5

Verilog, System Verilog, Python, Perl, Debugging, Vlsi, HDLs, RTL TB, SV UVM, Verdi

simvision , Cadence Tools, SV UVM-based mixed-signal testbench development, Xcelium, VIVA, Behavioral modeling using SV-RNM Verilog-AMS, SoC-AMS testbench development, Virtuoso ADE, Assembler

Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design

Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug

test environments , Test Cases, power-aware simulations, formal verification, DV testbenches, Design Verification, UVM methodology, power management features, coverage-driven verification, systemverilog

Perl, Python, UVM based verification environments, Verdi or equivalent debug tools, systemverilog