Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Scripting, Verdi, IUS, Uvm, GLS, systemverilog, debug tools, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Verilog, System Verilog, Asic verification, Uvm, cpu design, DDR4, Memory

Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Perl, Verilog, Python, VHDL, CDV, ABV, Uvm, SVA, systemverilog

Design Verification, Uvm, Verification Planning, systemverilog

Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols