arm architecture , AI ML SoC exposure, Gate-Level Simulation, Cadence Tools, Arm Corestone, ATE pattern generation support, Test Bench Development, SystemVerilog UVM, ASIC SOC verification, Low-power verification experience, Functional Verification, AXI AHB APB Protocols

Usb, C, Makefile, Windows, Shell, Pcie, Linux, Perl, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

C, Systemc, Windows, Usb, Linux, Makefile, Shell, Verilog, Ruby, System Verilog, Ethernet, Pcie, Perl, automating workflows in a distributed compute environment, graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, UVM based verification frameworks, simulation profile efficiency improvement

Test Plans, Nvme, DDR, Pcie, coverage analysis, UVM methodology, systemverilog, Axi, RTL debugging, testbenches, assertions, AHB

Verilog, Tcl, Python, Perl, VHDL, Uvm, systemverilog

simvision , Perl, Python, FineSim, Xcelium, UVM-based verification methodologies, WaveView, analog and mixed-signal circuits, DRAM memory architecture, systemverilog, SpectreFx, Hspice, PrimeSim, FastSpice tools, virtuoso

Windows, C, Systemc, Usb, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Ethernet, Perl, Pcie, Graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, simulation profile efficiency improvement, UVM based verification frameworks