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Job ID: 147211463
Skills:
Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog
Skills:
Git, Perl, Jira, Python, Uvm, systemverilog
Skills:
Python, Tcl, Analog mixed-signal IC design, behavioral modeling, systemverilog, Spectre, Rtl Design, Verification methodologies, Mixed-signal simulation tools, Verilog-AMS, AMS Designer, Cadence Virtuoso
Skills:
test environments , Machine Learning, Test Cases, Artificial Intelligence, industry-standard simulators, low-power design verification, regression systems, AI ML accelerators, vector processing units, systemverilog, revision control systems, verification testbenches, functional coverage, SVA
Skills:
Ethernet IEEE 802.3, waveform analysis, log tracing, Uvm, directed testing, systemverilog, functional and code coverage closure
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