Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog

Git, Perl, Jira, Python, Uvm, systemverilog

Python, Tcl, Analog mixed-signal IC design, behavioral modeling, systemverilog, Spectre, Rtl Design, Verification methodologies, Mixed-signal simulation tools, Verilog-AMS, AMS Designer, Cadence Virtuoso

test environments , Machine Learning, Test Cases, Artificial Intelligence, industry-standard simulators, low-power design verification, regression systems, AI ML accelerators, vector processing units, systemverilog, revision control systems, verification testbenches, functional coverage, SVA

Ethernet IEEE 802.3, waveform analysis, log tracing, Uvm, directed testing, systemverilog, functional and code coverage closure

Perl, Networking, AMBA

Jtag, C, Gpio, Uart, I2c, Spi, Flash, Timers, SWD, Axi, APB, AMBA protocols, Uvm, AHB, systemverilog, Assembly, BOOTROM, Sram