Design Verification Engineer

Job Description:

Role : Design Verification Engineer

Experience : 3+ Years

Location : Bangalore

Notice Period : Immediate Joiner

Preferred Skills:

• Strong Debug, UVM, System Verilog
• Understanding Specs and Standards and developing relevant test plans
• Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
• Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening
• Preferred Qualifications 3+ Year of industry experiences in the following areas: -
• Thorough understanding of Digital design concepts
• Thorough understanding dv methodologies and tools
• Good understanding of PCIe and CXL protocols is an added advantage
• Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI

Thanks

Kalyani P

[Confidential Information]

QTIMinds Private Limited

www.qtiminds.in