Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification

C, Debugging, Verilog RTL, Verification Techniques, Communication Interfaces, Scripting and Automation, EDA Tools, Uvm, Digital and SoC Verification, C DPI, systemverilog

System Verilog, Assertion-based verification, Cadence Xcelium, Power-aware verification, silicon debug, Gate-level simulation, Uvm, Synopsys VCS, Asic Design Verification, Synopsys JasperGold, Verification management tools, VC Formal

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog

Unix, Shell, Pcie, Linux, System Verilog, VIP coding, Coverage strategies and measurement, Constraint based Random verification, Skill, Test cases coding, Uvm, Digital Design and Verification methodologies, Python Script, DDR verification, Test Plan design

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Vcs, systemverilog, Questa, DDR Verification, Modelsim, Uvm

System Verilog, Coverage models, Uvm, Testbench design, DV methodology