Verilog, Ovm, System Verilog, Synopsys VCS, Cadence IES, VMM, formal property checking tools, Uvm

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Scripting, Verdi, IUS, Uvm, GLS, systemverilog, debug tools, Axi, IP SOC verification, Questa, CXL, CPU-based verification

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth

Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm

Design Verification, Uvm, Verification Planning, systemverilog

C++, Usb, Ethernet, Perl, engineering services, Asic verification

Unix, Shell, Linux, System Verilog, Pcie, VIP coding, Uvm, Python Script, Constraint based Random verification, Test cases coding, Coverage strategies and measurement, Test Plan design, Skill, DDR verification, Digital Design and Verification methodologies

Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols