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We are looking for a skilled Sr. Design Verification Engineer with strong hands-on experience in SV/UVM-based verification.
Key Requirements:
• Strong experience in SystemVerilog/UVM verification methodology
• Ability to derive verification features from specifications and create verification/test plans
• Hands-on experience in building testbench components from scratch
• Good exposure to IP/SoC level verification and coverage closure
• Strong knowledge of AMBA AHB protocol and debugging/root cause analysis
• Experience in writing assertions and handling functional/code coverage
Thanks,
Karthik
[Confidential Information]
Job ID: 147515525
Skills:
DDR, Usb, C, Pcie, Uart, I2c, Spi, Object-Oriented Programming, I3C, Uvm, systemverilog
Skills:
Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB
Skills:
Computer Architecture, System Verilog, Agentic AI, LLMs, Ai, Uvm
Skills:
Scripting Language, Usb, DDR, Pcie, Ethernet, Sata, System Verilog, Midi, Uvm, MIPI, CXL, LPDDR, 801.11, WiFi
Skills:
Makefile, Windows, Shell, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, debugging RTL code, systemverilog, acceleration, formal verification, testbenches, Efficiency Improvement, UVM-based verification frameworks
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