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Proficient in System Verilog and UVM, with the ability to build test case/environments.
Strong analytical and debugging skills; can work independently and drive projects end-to-end.
Atleast One High Speed Protocol (PCIe, Ethernet, DDR, LPDDR, USB, SATA, WiFi, MIDI, MIPI, CXL, 801.11 etc).
Collaborative communicator who works well across cross-functional teams.
Experience defining verification plans, developing UVM test benches, and driving coverage closure.
Familiarity with scripting language.
Job ID: 148276665
Skills:
Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB
Skills:
Makefile, Windows, Shell, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, debugging RTL code, systemverilog, acceleration, formal verification, testbenches, Efficiency Improvement, UVM-based verification frameworks
Skills:
Git, Perl, Jira, Python, Uvm, systemverilog
Skills:
Ethernet IEEE 802.3, waveform analysis, log tracing, Uvm, directed testing, systemverilog, functional and code coverage closure
Skills:
shell scripting, Verilog, Unix, Python, Uvm, VerilogAMS, systemverilog
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