Our client seeks a Verification Engineer to perform IP- level functional and performance verification in a UVM- based environment - This is a Direct and permanentRole.
Skills Required
Experience in UVM-based IP-level verification.
Strong Hands-on Expertise In
System Verilog and UVM methodology
RTL verification and debugging
Solid understanding of digital design concepts and verification methodologies.
Excellent communication and collaboration skills.
Ownership mindset with a focus on quality and timely delivery.
Nice To Have
Experience with NOC Subsystem
Good Knowledge of Memory Protocols DDR, LPDDR, HBM SystemC/ TLM modeling concepts
Experience with SystemC-RTL co-simulation setups.
Knowledge of profiling and performance analysis techniques.
Exposure to C++ modeling and high-level performance models.
Experience with scripting languages (Python, Perl, Shell) for automation.
Responsibilities
Develop and maintain UVM-based verification environments for complex IP blocks, ensuring comprehensive functional coverage.
Create, execute, and debug testcases in System Verilog to validate RTL functionality and identify design issues early in the cycle.
Analyze design specifications and define verification plans, coverage goals, and test strategies aligned with project requirements.
Collaborate closely with design, architecture, and validation teams to drive resolution of functional bugs and ensure high-quality deliverables.
Continuously improve verification workflows by enhancing testbench components, refining methodologies, and promoting best practices.
