Design Verification Engineer

test environments , Test Cases, Regression systems, Low-power design verification, Industry-standard simulators, Verification methodology, Revision control systems, Verification testbenches, Functional coverage, systemverilog

Makefile, Windows, Linux, Perl, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, Efficiency Improvement, UVM-based verification frameworks

Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog

DDR, Pcie, System Verilog, HBM, Uvm, UCIe

Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB