C
Design Verification Engineer
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Capgemini was founded by Serge Kampf in 1967 as an enterprise management and data processing company. The company was founded as the Société pour la Gestion de l'Entreprise et le Traitement de l'Information (Sogeti).In 1974 Sogeti acquired Gemini Computers Systems, a US company based in New York.In 1975, having made two major acquisitions of CAP (Centre d'Analyse et de Programmation) and Gemini Computer Systems, and following resolution of a dispute with the similarly named CAP UK over the international use of the name 'CAP', Sogeti renamed itself as CAP Gemini Sogeti.
Job ID: 150131619
Skills:
simvision , Cadence Tools, SV UVM-based mixed-signal testbench development, Xcelium, VIVA, Behavioral modeling using SV-RNM Verilog-AMS, SoC-AMS testbench development, Virtuoso ADE, Assembler
Skills:
Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design
Skills:
Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug
Skills:
wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies
Skills:
C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency
