Fpga, Vcs, Pcie, Ethernet, Xcelium, Emulation, Uvm, systemverilog, Dft, Questa, DDR5, DDR4

Programming Languages, Architecture and design tools, Design verification methods, Scripting tools, RTL to GDS Flow, virtuoso

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

Perl, Ruby, System Verilog, Asic verification, Rtl Design, make, Uvm, formal verification, TestBench Development

Verilog, Matlab, Python, FPGA-based emulation, DSP concepts

Perl, Ruby, System Verilog, make, Uvm

Verilog, Python, Synopsys, Cadence Tools, performance modeling tools, low power design techniques, arithmetic units, accelerators, memory hierarchies, bus architectures

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Verilog, cdc, VHDL, RDC, Test plan creation and execution, Formal verification methodologies, Uvm, Constrained random verification techniques, systemverilog