AI ML accelerators, systemverilog, vector processing units, functional coverage

Verilog, Python, Tcl, UVM verification methodology, Synopsys VCS, VHDL, Cadence Xcelium, Questa, systemverilog

circuit simulation tools, analog circuit design principles, power performance and area optimizations, advanced process nodes

Makefile, Windows, Linux, Perl, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, Efficiency Improvement, UVM-based verification frameworks

Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog

Makefile, Windows, Perl, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, UVM-based verification frameworks

Test Plan Creation, Verilog, AHB, Uvm, UPF, DV environments, BFM, constrained random verification techniques, APB bus protocols, systemverilog, cdc, VHDL, CPF, block functional models, formal verification methodologies, RDC, Execution

DDR, Usb, C, Pcie, Uart, I2c, Spi, Object-Oriented Programming, I3C, Uvm, systemverilog

DDR, Pcie, System Verilog, HBM, Uvm, UCIe