Ovm, Verilog, System Verilog, DFI protocol, formal verification, Jedec standards, Functional Verification Coverage, Design Verification, Uvm, Low Power Verification, Gate Simulation

code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage

Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, Synopsys VCS, APB, EDA Tools, CRI, IJTAG

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

C, Coding, Performance Modeling, low power design verification techniques, coverage planning, power management verification, testbench development, systemverilog, coverage closure, GLS power aware verification, Asic Design Verification, ACPI standards, post-si verification, Validation

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

Python Scripting, Jasper, Verilog, System Verilog, formal verification, VC-FORMAL, SVA