Design Verification Engineer

This is an excellent opportunity to be part of a growing team with visibility and access across the company's Business Units developing a wide range of leading-edge IC solutions that require or benefit from Secure HW/FW/SW.

• Responsibilities include but not limited to:
• Architect, document, and build UVM test benches to verify blocks, subsystems, and SOC level IP
• Develop test plans based on Requirements and HW design specifications
• Work within a UVM System Verilog environment to develop tests achieving high coverage vs. specification and use cases
• Debug and solve complex problems that require GLS, AMS DV collaboration, lab evaluation issue recreation, and fault injection/detection techniques
• Lead and become technical mentor to local DV team
• Continual review and improvement of verification methodology and tools
• Actively track and proactively communicate status to extended team and management using Agile development practices
• The ideal candidate will meet the following requirements:
• 7+ years digital verification experience
• Expert-level knowledge in System Verilog and UVM
• AI enabled DV development including testbench, rootcause analysis and coverage closure
• Experience profile applying DV techniques in the following areas:
• Legacy and Post Quantum crypto accelerators in SW, HW, and mixed mode domains
• Portable testing navigating block, subsystem, and chip level verification environments
• MCU-based digital and mixed signal SOC's
• FPGA, HW emulation, SystemC platforms
• Experience with languages such as Python, SystemC, C/C++
• Experience leading DV teams embedded into larger cross-functional product development teams
• Able to set priorities, deliver on commitments, work autonomously
• Reuse mindset and demonstrated experience
• BSEE/MSEE