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We're Hiring: Design Verification Engineer (VLSI)
Company: ACL Digital
Location: Bangalore
Experience: 4+ Years
ACL Digital is looking for skilled Design Verification Engineers to join our growing VLSI team. If you're passionate about verification, debugging complex designs, and working on advanced semiconductor technologies, we'd love to connect with you!
Key Responsibilities:
Required Skills:
Qualifications:
Good to Have:
Why Join ACL Digital
Interested candidates can share their resume at: [Confidential Information]
#Hiring #VLSI #DesignVerification #SystemVerilog #UVM #Semiconductors #BangaloreJobs #EngineeringJobs
Job ID: 147027555
Skills:
C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, Validation using Emulation and FPGA HW platforms, cache controllers, x86 assembly, semi randomized test generators, Uvm, systemverilog, validation strategy development, memory coherency, debugging test failures, power management, AI based methodologies in Validation, coverage driven Validation methodologies
Skills:
Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, Cadence Xcelium, VHDL, Uvm, SVA, systemverilog
Skills:
Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB
Skills:
bandwidth management , Microprocessor Cores, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, packet processing, Verification, congestion control, systemverilog, constrained-random verification
Skills:
Computer Architecture, Debugging, Uvm, systemverilog, Coverage-Driven Verification, Constrained-Random Testing, formal verification, Functional Verification, Testbench Development, Verification Planning, Formal Tools, Rtl Design
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