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ALTEN Calsoft Labs

Design Verification Engineer

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  • Posted 7 hours ago
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Job Description

We're Hiring: Design Verification Engineer (VLSI)

Company: ACL Digital

Location: Bangalore

Experience: 4+ Years

ACL Digital is looking for skilled Design Verification Engineers to join our growing VLSI team. If you're passionate about verification, debugging complex designs, and working on advanced semiconductor technologies, we'd love to connect with you!

Key Responsibilities:

  • Develop and execute comprehensive verification plans for complex SoC/IP designs
  • Build and maintain scalable testbenches using SystemVerilog and UVM
  • Perform functional verification, debug issues, and analyze coverage metrics
  • Collaborate closely with design and architecture teams to ensure design quality
  • Run regressions, analyze failures, and drive closure of verification goals
  • Contribute to methodology improvements and automation

Required Skills:

  • Strong fundamentals in digital design and verification concepts
  • Hands-on experience with SystemVerilog and UVM
  • Experience in RTL verification, debugging, and coverage-driven verification
  • Familiarity with simulators like VCS / Questa / Xcelium
  • Knowledge of scripting languages such as Python or Shell
  • Experience with standard protocols (AXI, AHB, APB, PCIe, I2C, SPI, etc.)

Qualifications:

  • Bachelor's or Master's degree in Electronics / Electrical Engineering or related field

Good to Have:

  • Experience in SoC-level verification
  • Exposure to low-power verification (UPF/CPF)
  • Knowledge of formal verification techniques
  • Experience with emulation or FPGA prototyping

Why Join ACL Digital

  • Opportunity to work on cutting-edge semiconductor projects
  • Collaborative and innovation-driven work environment
  • Strong growth and learning opportunities

Interested candidates can share their resume at: [Confidential Information]

#Hiring #VLSI #DesignVerification #SystemVerilog #UVM #Semiconductors #BangaloreJobs #EngineeringJobs

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Job ID: 147027555

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