C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, Validation using Emulation and FPGA HW platforms, cache controllers, x86 assembly, semi randomized test generators, Uvm, systemverilog, validation strategy development, memory coherency, debugging test failures, power management, AI based methodologies in Validation, coverage driven Validation methodologies

Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, Cadence Xcelium, VHDL, Uvm, SVA, systemverilog

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB

bandwidth management , Microprocessor Cores, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, packet processing, Verification, congestion control, systemverilog, constrained-random verification

Computer Architecture, Debugging, Uvm, systemverilog, Coverage-Driven Verification, Constrained-Random Testing, formal verification, Functional Verification, Testbench Development, Verification Planning, Formal Tools, Rtl Design