Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols

Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA