Design Verification Engineer

#ACL Digital is Hiring: GPM Subsystem Verification Engineer

Must-have: UVM, System Verilog, IP Verification

Preferred: Power Management IP, Firmware DV, Python/Perl

Full-cycle DV: test plan tape out

Collaborate with top DV, design & architecture teams

Apply/Refer: [Confidential Information]

#ACLDigital#HiringNow#DesignVerification#UVM#SystemVerilog

#PowerManagementIP#HyderabadJobs#VLSICareers