Design Lead
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Job Description
Job Overview
Join Tessolve, a leading player in digital engineering and design services, as a Senior Verification Engineer. Contribute by verifying IP and SOC interfaces using SystemVerilog and advanced verification methodologies. Play a key role in integrating virtual interface peripherals, ensuring high-speed serial and SOC interfaces are efficiently verified. Engage in a multinational environment, contributing to advanced silicon products that serve top industry clients. Enhance your career by leveraging Tessolve's global presence and cutting-edge testing infrastructure.
Job Designation : Senior Verification Engineer
Years of Exp: 8 to 15 years
Job Location: Global (Tessolve offices worldwide)
What You'll Do
Join Tessolve, a leading player in digital engineering and design services, as a Senior Verification Engineer. Contribute by verifying IP and SOC interfaces using SystemVerilog and advanced verification methodologies. Play a key role in integrating virtual interface peripherals, ensuring high-speed serial and SOC interfaces are efficiently verified. Engage in a multinational environment, contributing to advanced silicon products that serve top industry clients. Enhance your career by leveraging Tessolve's global presence and cutting-edge testing infrastructure.
Job Designation : Senior Verification Engineer
Years of Exp: 8 to 15 years
Job Location: Global (Tessolve offices worldwide)
What You'll Do
- Verify IP and SOC interfaces using SystemVerilog (SV) and UVM methodologies
- Integrate and verify virtual interface peripherals in silicon designs
- Ensure coverage closure, including code and functional aspects
- Prepare technical documentation, including testbench and test plan specifications
- IP verification Using SV/UVM
- Interconnect Protocols: .DDR/PCIe/Mipi/USB/ Ethernet/CXL/UCI/UFS
- High Speed Serial Interfaces: PCIe or UCIe or USB or Ethernet or UPF or DDR
- Coverage Closure: Code, Functional and Toggle
- Tools: Synopsys VCS or Cadence Incisive
- Technical Documentation: Testbench Specification, Test Plan Specification
- Good exposure to Scripting skills like Perl or Python or Shell or TCL
- Bachelors in Electronics Engineering is a minimum requirement
- Masters in Electronics or Computer Science Engineering is an added advantage
- 8 to 15 years minimum
- Exposure to working in multi-national environment is required
- Excellent oral and written communication skills is a must.
- An attitude to learn and grow. Adaptability and flexibility are desired.
More Info
Job Type:
Industry:
Employment Type:
Key Skills
Synopsys VCS
High Speed Serial Interfaces
Cadence Incisive
IP verification
Coverage Closure
Interconnect Protocols
About Company
Skills:
low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks
Skills:
Verilog, power analysis, design of SoCs, Synthesis, VHDL, Design Verification, Chisel, micro-architecture, ASIC development, systemverilog
Skills:
low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks
Skills:
Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification
Skills:
Pcie, timing-aware micro-architecture, high-throughput datapath, deskew, SystemVerilog RTL, design-for-test, Digital Design, UCIe, high-speed lane alignment, physical-closure collaboration, SERDES, CXL, micro-architecture