low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

Verilog, power analysis, design of SoCs, Synthesis, VHDL, Design Verification, Chisel, micro-architecture, ASIC development, systemverilog

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

Pcie, timing-aware micro-architecture, high-throughput datapath, deskew, SystemVerilog RTL, design-for-test, Digital Design, UCIe, high-speed lane alignment, physical-closure collaboration, SERDES, CXL, micro-architecture

Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model

shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog

code coverage , Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, IP or SoC verification, SV METH, C tests, SV OOPS, spyglass, Axi, AMBA, VHDL, Graphics, RTL Coding, ARM based SoC verification, AHB